The present invention relates to a communication device, a communication method, and a recording medium for recording a program employed to carry out the communication method. More particularly, the present invention relates to a communication device which is capable of reducing noises due to higher harmonic components of a clock so as to avoid the disturbance over its receiving function and its transmitting function by setting an oscillation frequency of the clock easily at a high speed and with high precision such that the higher harmonic components of the clock which drives processing means such as LSI""s being built in the communication device can go farthest from a receiving frequency or a transmitting frequency, a communication method of operating the communication device, and a recording medium.
In recent years, in various communication devices having the receiving function and the transmitting function, a microcomputer, a digital signal processor (DSP), or special-purpose LSI""s, etc. are incorporated and also an oscillating means for oscillating an LSI operation clock to drive these LSI""s is provided. However, this LSI operation clock contains many higher harmonic components. When mixed into a receiving band or a transmitting band, the higher harmonic components disturb the receiving function and the transmitting function. For this reason, several techniques which avoid noises due to the LSI operation clock have been proposed in the prior art.
FIG. 9 is a schematic view showing a configuration of xe2x80x9cA receiver device equipped with a clock oscillator circuitxe2x80x9d disclosed in Unexamined Patent Application Publication Hei 8-102689 (first prior art). In FIG. 9, the receiver device comprises a receiver portion 506 having a received data decision circuit 507, a control voltage generator portion 505, and an oscillator circuit portion. The oscillator circuit portion comprises a crystal oscillator 501, an inverter 502, a capacitor 503, a variable capacitor (variable capacity diode) 504, and a resistor R.
The crystal oscillator 501 is caused by the inverter 502 to oscillate. According to capacitance values of the capacitor 503 and the variable capacitor 504, an oscillation frequency of an operation clock CLK5, which is generated by the oscillator circuit portion, can be decided. In this case, the capacitance of the variable capacitor 504 can be controlled by a control voltage which is output from the control voltage generator portion 505, and the control voltage can be decided based on information from the received data decision circuit 507 of the receiver portion 506.
Next, an operation of the receiver device in the first prior art will be explained hereunder. First, the received data decision circuit 507 of the receiver portion 506 makes decision of the received data during reception and then detects whether or not disturbance due to the operation noise of the microcomputer built in the receiver device is caused. If the disturbance is detected at that time, the received data decision circuit 507 outputs a control signal CTL5 to the control voltage generator portion 505 so as to change the control voltage, which is output from the control voltage generator portion 505, such that the oscillation frequency of the operation clock CLK5 can be slightly changed. Then, the oscillation frequency of the operation clock CLK5 of the microcomputer is still changed until such disturbance cannot be detected, so that degradation of the radio performance (receiving function) of the receiver device can be avoided.
Also, FIG. 10 shows a configuration of another receiver device having a noise canceling function (second prior art). In FIG. 10, the receiver device comprises a microcomputer 607 and the oscillator circuit portion. The oscillator circuit portion comprises a crystal oscillator 601, an inverter 602, capacitors 603, 604, a variable capacitor 605, a transistor 606, and the resistor R.
The crystal oscillator 601 is caused by the inverter 502 to oscillate. According to capacitance values of the capacitor 603 and 604, an oscillation frequency of an operation clock CLK6, which is generated by the oscillator circuit portion, can be decided. However, if the microcomputer 607 causes the transistor 606 to turn ON via a control signal CTL6, the oscillation frequency of the operation clock CLK6 can be decided based on a total capacitance value of the capacitance values of the capacitor 603, 604 and the capacitance value of the variable capacitor 605.
Next, an operation of the receiver device in the second prior art will be explained hereunder. First, normally the microcomputer 607 outputs an xe2x80x9cLxe2x80x9d level signal as the control signal CTL6 and then turns OFF the transistor 606 via the resistor R. At that time, the oscillation frequency of the operation clock CLK6 supplied to the microcomputer 607 can be decided according to the capacitance values of the capacitors 603 and 604 in the oscillator circuit portion. However, in the event that higher harmonics of the oscillation frequency of the operation clock CLK6 exist in the neighborhood of a receiving frequency to thus cause the degradation of the radio performance (receiving function), the microcomputer 607 outputs an xe2x80x9cHxe2x80x9d level signal as the control signal CTL6 to shift the transistor 606 into its ON state. Accordingly, the oscillation frequency of the operation clock CLK6 can be changed into a frequency which is decided by the capacitance values of the capacitors 603, 604 and the variable capacitor 605 in the oscillator circuit portion. Thus, the higher harmonics of the oscillation frequency of the operation clock CLK6 are separated away from the neighborhood of the receiving frequency, so that degradation of the radio performance (receiving function) can be prevented.
However, in the above receiver device in the first prior art, since the control voltage of the control voltage generator portion 505 is decided based on the decision result of the received data decision circuit 507 of the receiver portion 506, a time is needed to some extent until the control voltage has been decided. As a result, there have been the problems such that the response is not good until change/adjustment of the oscillation frequency of the operation clock CLK has been completed and that the period which is contained within a predetermined time but has low reliability of the received data still remains.
Furthermore, in the above receiver device in the second prior art, since the capacitance values in the oscillator circuit portion are changed according to the ON/OFF control of the transistor 606 based on the control signal CTL6, adjustment precision of the oscillation frequency is very rough. Thus, there have been the problems that it is difficult to adjust the higher harmonic components of the operation clock CLK6 of the microcomputer 607 so as to go away from the receiving frequency and that deterioration of the radio performance (receiving function) cannot be perfectly prevented.
The present invention has been made in view of the above problems in the prior art, and it is an object of the present invention to provide a communication device which is capable of reducing noises due to higher harmonic components of a clock and also avoiding the disturbance over its receiving function and its transmitting function by setting an oscillation frequency of the clock easily at a high speed and with high precision such that the higher harmonic components of the clock for driving processing means such as LSI""s built in the communication device can positioned farthest from a receiving frequency or a transmitting frequency, a communication method of operating the communication device, and a recording medium.
In order to overcome the above subjects, according to first aspect of the present invention, a communication device comprises a clock generating means for generating a clock, a processing means which operates based on the clock, and a radio portion for processing a radio signal at a predetermined receiving frequency, an operation frequency controlling means for calculating an operation frequency of the clock such that higher harmonics of the operation frequency of the clock is positioned farthest from the radio frequency; wherein the clock generating means generates the clock having the operation frequency calculated by the operation frequency controlling means.
In the present invention, the radio portion may be a receiver portion for receiving a signal transmitted from another communication device at a predetermined receiving frequency and demodulating it, and the operation frequency controlling means calculates an operation frequency of the clock such that higher harmonics of the operation frequency of the clock can be positioned farthest from the receiving frequency and the clock generating means generates the clock having the operation frequency calculated by the operation frequency controlling means.
Also, the radio portion may be a transmitter portion for transmitting a transmit signal modulated at a predetermined transmitting frequency, and the operation frequency controlling means calculates an operation frequency of the clock such that higher harmonics of the operation frequency of the clock can be positioned farthest from the transmitting frequency; wherein the clock generating means generates the clock having the operation frequency calculated by the operation frequency controlling means.
Also,the radio portion may include a receiver portion for receiving a signal transmitted from another communication device at a predetermined receiving frequency and demodulating it, and a transmitter portion for transmitting a transmit signal modulated at a predetermined transmitting frequency, and the operation frequency controlling means calculates an operation frequency of the clock such that higher harmonics of the operation frequency of the clock can be positioned farthest from the receiving frequency or the transmitting frequency; wherein the clock generating means generates the clock having the operation frequency calculated by the operation frequency controlling means.
Preferably, in the communication device according to the present invention, the clock generating means is composed of a PLL frequency synthesizer which comprises a reference oscillator, a phase comparator, a low pass filter, a voltage controlled oscillator, and a variable frequency divider, and which varies the operation frequency of the clock by programmably changing a frequency dividing ratio of the variable frequency divider.
Preferably, the communication device according to the present invention further comprises a storing means for holding calculation results of the operation frequency of the clock whose higher harmonics can be positioned farthest from the receiving frequency or the transmitting frequency every receiving frequency or every transmitting frequency.
According to the second aspect of the present invention, there is provided a communication method for a communication device including a clock generating means for generating a clock, a processing means which operates based on the clock, and a radio portion for processing a radio signal at a predetermined frequency, the communication method comprising an operation frequency controlling step of calculating an operation frequency of the clock such that higher harmonics of the operation frequency of the clock can be positioned farthest from the radio frequency; wherein the clock generating means generates the clock having the operation frequency calculated by the operation frequency controlling step.
Preferably, the radio portion may be a receiver portion for receiving a signal transmitted from another communication device at a predetermined receiving frequency and demodulating it, and an operation frequency of the clock is calculated such that higher harmonics of the operation frequency of the clock can be positioned farthest from the receiving frequency.
Also, the radio portion may be a transmitter portion for transmitting a transmit signal modulated at a predetermined transmitting frequency, and an operation frequency of the clock is calculated such that higher harmonics of the operation frequency of the clock can be positioned farthest from the transmitting frequency
Also, the radio portion may include a receiver portion for receiving a signal transmitted from another communication device at a predetermined receiving frequency and demodulating it, and a transmitter portion for transmitting a transmit signal modulated at a predetermined transmitting frequency, an operation frequency of the clock is calculated such that higher harmonics of the operation frequency of the clock can be positioned farthest from the receiving frequency or the transmitting frequency.
Preferably, in the communication method according to the present invention, the clock generating means is composed of a PLL frequency synthesizer which comprises a reference oscillator, a phase comparator, a low pass filter, a voltage controlled oscillator, and a variable frequency divider, and the operation frequency controlling step has a varying step of varying the operation frequency of the clock by setting a frequency dividing ratio into the variable frequency divider in accordance with a calculated operation frequency.
Preferably, the communication method further comprises a calculating step of calculating the operation frequency of the clock whose higher harmonics can be positioned farthest from the receiving frequency or the transmitting frequency every receiving frequency or every transmitting frequency; and a storing step of holding results calculated in the calculating step in a storing means.
Preferably, the operation frequency controlling step or the calculating step includes a first calculating step of calculating frequency difference between the higher harmonics, which can be positioned nearest to the receiving frequency or the transmitting frequency, out of the higher harmonics of the operation frequency of the clock and the receiving frequency or the transmitting frequency every operation frequency of the clock, which can be set in the clock generating means, and a second calculating step of identifying the higher harmonics, which has a maximum frequency difference out of frequency differences between higher harmonics which are calculated by the first calculating step and the receiving frequency or the transmitting frequency and then calculating the operation frequency of the clock corresponding to an identified higher harmonics.
In addition, there is provided a computer readable recording medium for recording the communication method set forth above as a program which causes a computer to carry out the communication method.
According to the present invention, the operation frequency of the clock is calculated by the operation frequency controlling means (operation frequency controlling step) such that the higher harmonics of the operation frequency of the clock can be positioned farthest from the receiving frequency or the transmitting frequency, and then the clock having the operation frequency calculated by the operation frequency controlling means (operation frequency controlling step) is generated by the clock generating means.
Where the xe2x80x9cclockxe2x80x9d is generated by the clock generating means, and the communication device employs the clock to drive or operate the built-in processing means which executes control, analysis, etc. of the process. The microcomputer (microprocessor), the digital signal processor (DSP), the special-purpose LSI, or the like correspond to the xe2x80x9cprocessing meansxe2x80x9d. Also, the operation frequency controlling means can be implemented by the above processing means, for example, and also the operation frequency controlling step can be implemented by the program carried out by the processing means.
In this way, the oscillation frequency of the clock is calculated by the operation frequency controlling means (operation frequency controlling step) such that the higher harmonics of the operation frequency of the clock can be positioned farthest from the receiving frequency or the transmitting frequency, and then the clock having the calculated operation frequency is generated by the clock generating means such as the PLL frequency synthesizer. Therefore, the oscillation frequency of the clock can be set easily at a high speed and with high precision such that the higher harmonic components of the clock which drives the processing means built in the communication device can be positioned farthest from the receiving frequency or the transmitting frequency. As a result, the noises due to the higher harmonic components of the operation clock can be reduced, the disturbance over the receiving function or the transmitting function of the communication device can be avoided, and deterioration of the radio performance can be completely prevented.
Especially, the clock generating means is composed of the PLL frequency synthesizer which comprises the reference oscillator, the phase comparator, the low pass filter, the voltage controlled oscillator, and the variable frequency divider. In the operation frequency controlling means (operation frequency controlling step), the operation frequency of the clock is varied by setting the frequency dividing ratio, which correspond to the calculated operation frequency, into the variable frequency divider (by the changing step).
In this fashion, since the clock generating means is constructed by the programmable PLL frequency synthesizer, the frequency variable range can be set wide and the frequency change can be made easy. Also, since the crystal oscillator is employed as the reference oscillator 101 to generate the reference signal (reference frequency), the operation frequency can be adjusted with extremely high precision.
Also, the operation frequency of the clock whose higher harmonics can be positioned farthest from the receiving frequency or the transmitting frequency is calculated (by the calculating step) every receiving frequency or every transmitting frequency, and the results calculated (by the calculating step) are held in the storing means (in the storing step). In this case, this process (carried out by the calculating step and the storing step) may be conducted by either the operation frequency controlling means (operation frequency controlling step) or the external processing means of the communication device.
Likewise, the operation frequency of the clock is calculated previously relative to each receiving frequency or each transmitting frequency and then held in the storing means. Therefore, the oscillation frequency of the clock, which is able to reduce the noises due to the higher harmonic components and avoid the disturbance over the receiving function or the transmitting function, can be set easily at a higher speed and with high precision according to the receiving frequency or the transmitting frequency.
In addition, in the operation frequency controlling step or the calculating step, frequency difference between the higher harmonics, which can be positioned nearest to the receiving frequency or the transmitting frequency, out of the higher harmonics of the operation frequency of the clock and the receiving frequency or the transmitting frequency is calculated by the first calculating step every operation frequency of the clock, which can be set in the clock generating means, and then the higher harmonics which has a maximum frequency difference out of frequency differences between higher harmonics which are calculated by the first calculating step and the receiving frequency or the transmitting frequency is identified and then the operation frequency of the clock corresponding to an identified higher harmonics is calculated by the second calculating step.